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Sunday, December 16, 2018

Coreboot X220 guide

Please read the post Neuter Intel ME with me_cleaner which describes how to read and write BIOS chips with an SPI programmer - this will not be covered here. This guide is written for a Linux system.

Basic steps are
  1. Obtain a copy of Coreboot and submodules
  2. Build needed tools
  3. Create optional blobs
  4. Configure Coreboot and payload settings
  5. Make Coreboot image
  6. Flash image 
Things to note
  • Coreboot can apply me_cleaner automatically.
  • Coreboot will make Thinkpad Power Manager, and Hotkey Manager non-functional in Windows.
  • You will loose some features from Lenovo BIOS e.g. ATA/startup/BIOS passwords, enabling/disabling ports, advanced or unlocked BIOS options, Windows licenses.

Obtain Coreboot

Run the following code

git clone http://review.coreboot.org/coreboot.git ~/coreboot 
cd ~/coreboot 
git submodule update --init --recursive 

Build Tools

We now need to build ifdtool, gcc, and iasl needed to compile Coreboot binaries.

cd ~/coreboot/util/ifdtool 
cd ~/coreboot 
make crossgcc-i386

This will take a while. An example output log can be found at the bottom of the post.


We will require some proprietary blobs from the Lenovo BIOS required to initialize proprietary Intel components in the chipset. We can do this using ifdtool.

First move the firmware that was read using the SPI programmer to the ifdtool directory ~/coreboot/util/ifdtool Then run

ifdtool -x original.bin # original.bin is the firmware you read from the motherboard

This will create these files in the current directory


We will then move these to the directory that coreboot will look in.

mkdir -p ~/coreboot/3rdparty/blobs/mainboard/lenovo/x220
cd ~/coreboot/3rdparty/blobs/mainboard/lenovo/x220
mv ~/flashregion_0_flashdescriptor.bin descriptor.bin
mv ~/flashregion_2_intel_me.bin me.bin
mv ~/flashregion_3_gbe.bin gbe.bin 

We will also require a VGA BIOS for graphics within the console and for Windows compatibility. If you only plan on running Linux this is optional as the kernel will take care of it. For this step we will need the orignal X220 BIOS from Lenovo and uefitool.

git clone https://github.com/LongSoft/UEFITool.git ~/coreboot/util/uefitool
cp [location of $01CB000.FL1 from extracted Lenovo firmware update] ~/coreboot/util/uefitool
uefitool $01CB000.FL1

Then do the following
  1. Open the search tool in uefitool, select Text mode, uncheck Unicode, and search for the string, "VGA Compatible BIOS". 
  2. Double click on the result. This will bring you to the section where this string is found. 
  3. Right click on the highlighted section and click "Extract Body".
  4. Save the file as vbios.bin in ~/coreboot/3rdparty/blobs/mainboard/lenovo/x220
  5. Quit uefitool
We now have all the bits we need to compile Coreboot

Configure Coreboot

Run the following

cd ~/coreboot
make nconfig

This screen will allow us to configure Coreboot settings, drivers, payloads etc. Read the helpful setting description using the F2 key. I used the following settings. If the option is not shown below, it is not set or the default setting. Seabios is the recommended payload (program to boot an OS).

[*] Compress ramstage with LZMA
[*] Include the coreboot .config file into the ROM image
[*] Create a table of timestamps collected during boot

Mainboard vendor (Lenovo) --->
Mainboard model (ThinkPad X220) --->
ROM chip size (8192 KB (8 MB)) --->

[*] Enable VMX for virtualization
[*] Set lock bit after configuring VMX
Include CPU microcode in CBFS (Generate from tree) --->
*** Northbridge ***
[*] Use native raminit
[*] Ignore vendor programmed fuses that limit max. DRAM frequency
*** Southbridge ***
[*] Lock down chipset in coreboot
*** Super I/O ***
*** Embedded Controllers ***
[*] Beep on fatal error
[*] Flash LEDs on fatal error
*** Intel Firmware ***
[*] Add Intel descriptor.bin file
(3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) Path and
[*] Add Intel ME/TXE firmware
(3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) Path to manageme
[*] Verify the integrity of the supplied ME/TXE firmware
[*] Strip down the Intel ME/TXE firmware
*** Please test the modified ME/TXE firmware and coreboot in
[*] Add gigabit ethernet firmware
(3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) Path to gigabit

Graphics initialization (Run VGA Option ROMs)--->
[*] Re-run VGA Option ROMs on S3 resume
[*] Load Option ROMs on PCI devices
Option ROM execution type (Native mode)--->
-*- Enable PCIe Common Clock
-*- Enable PCIe ASPM
[*] Enable PCIe Clock Power Management
[*] Enable PCIe ASPM L1 SubState
[*] Add a VGA BIOS image
(3rdparty/blobs/mainboard/lenovo/x220/vbios.bin) VGA BIOS path and f
(8086,0126) VGA device PCI IDs
[*] Add a Video Bios Table (VBT) binary to CBFS
(src/mainboard/$(MAINBOARDDIR)/data.vbt) VBT binary path and filen

Generic Drivers
[*] Support Intel PCI-e WiFi adapters
[*] PS/2 keyboard init  

[*] Use onboard VGA as primary video device  

System Tables
[*] Generate SMBIOS tables  

Add a payload (SeaBIOS)--->
SeaBIOS version (1.12.0)--->
(3000) PS/2 keyboard controller initialization timeout (millisecon
[*] Hardware init during option ROM execution
Payload compression algorithm (Use LZMA compression for payloads)
[*] Use LZMA compression for secondary payloads
Secondary Payloads--->
 [*] Load coreinfo as a secondary payload
[*] Load Memtest86+ as a secondary payload
[*] Load nvramcui as a secondary payload
[*] Load tint as a secondary payload
Memtest86+ version (Stable)--->

Save the config (F6) then Exit (F9). We can now compile Coreboot. Run


If all goes well we well you will see

Built lenovo/x220 (ThinkPad X220)

...and have a Coreboot image ~/coreboot/build/coreboot.rom

Flash the Image

Follow the instructions to flash coreboot.rom here, and hope that it works.


You now have Coreboot on your system!

Log Dumps

Note - these logs are likely to be different to yours. Some steps are not shown.

[x220@x220 ifdtool]$ ifdtool -x original.bin
File original.bin is 8388608 bytes
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00500000 - 007fffff
Flash Region 2 (Intel ME): 00003000 - 004fffff
Flash Region 3 (GbE): 00001000 - 00002fff
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

[x220@x220 coreboot]$ make crossgcc-i386
fatal: not a git repository (or any of the parent directories): .git
Welcome to the coreboot cross toolchain builder v1.53 (August 16th, 2018)

Building toolchain using 4 thread(s).

Target architecture is i386-elf

No compatible Ada compiler (GNAT) found. You can continue without
Ada support, but this will limit the features of coreboot (e.g.
native graphics initialization won't be available on most Intel

Usually, you can install GNAT with your package management system
(the package is called `gnat` or `gcc-ada`). It has to match the
`gcc` package in version. If there are multiple versions of GCC in-
stalled, you can point this script to the matching version through
the `CC` and `CXX` environment variables.

e.g. on Ubuntu 14.04, if `gcc` is `gcc-4.8`:
apt-get install gnat-4.8 && make crossgcc

on Ubuntu 16.04, if `gcc` is `gcc-5`:
apt-get install gnat-5 && make crossgcc

Press Ctrl-C to abort, Enter to continue... 13s
Downloading and verifing tarballs ...
* gmp-6.1.2.tar.xz (downloading from https://ftpmirror.gnu.org/gmp/gmp-6.1.2.tar.xz)... 100%... hash verified ("9dc6981197a7d92f339192eea974f5eca48fcffe")
* mpfr-3.1.5.tar.xz (downloading from https://ftpmirror.gnu.org/mpfr/mpfr-3.1.5.tar.xz)... 100%... hash verified ("c0fab77c6da4cb710c81cc04092fb9bea11a9403")
* mpc-1.0.3.tar.gz (downloading from https://ftpmirror.gnu.org/mpc/mpc-1.0.3.tar.gz)... 100%... hash verified ("b8be66396c726fdc36ebb0f692ed8a8cca3bcc66")
* binutils-2.30.tar.xz (downloading from https://ftpmirror.gnu.org/binutils/binutils-2.30.tar.xz)... 100%... hash verified ("574d3b5650413d6ee65195a4f5ecbddc3a38f718")
* gcc-8.1.0.tar.xz (downloading from https://ftpmirror.gnu.org/gcc/gcc-8.1.0/gcc-8.1.0.tar.xz)... 100%... hash verified ("b34031ba9ff3e248b2c62de0825e49a1e0e01998")
Downloaded tarballs ... ok
Unpacking and patching ...
* gmp-6.1.2.tar.xz
o gmp-6.1.2_freebsd-configure.patch
* mpfr-3.1.5.tar.xz
* mpc-1.0.3.tar.gz
* binutils-2.30.tar.xz
o binutils-2.30_mips-gold.patch
o binutils-2.30_nds32.patch
o binutils-2.30_no-bfd-doc.patch
* gcc-8.1.0.tar.xz
o gcc-8.1.0_ada-musl_workaround.patch
o gcc-8.1.0_armv6s-m.patch
o gcc-8.1.0_bsd.patch
o gcc-8.1.0_gnat.patch
o gcc-8.1.0_libgcc.patch
o gcc-8.1.0_nds32_ite.patch
Unpacked and patched ... ok
Building packages ...
Building GMP v6.1.2 for host ... ok
Building MPFR v3.1.5 for host ... ok
Building MPC v1.0.3 for host ... ok
Building BINUTILS v2.30 for target ... ok
Building GCC v8.1.0 for target ... ok
Packages built ... ok
Copied EDK2 tools template ... ok
Cleaning up temporary files... ok

You can now run i386-elf cross GCC from /home/x220/coreboot/util/crossgcc/xgcc.
fatal: not a git repository (or any of the parent directories): .git
Welcome to the coreboot cross toolchain builder v1.53 (August 16th, 2018)

Building toolchain using 4 thread(s).

Downloading and verifing tarballs ...
* acpica-unix2-20180810.tar.gz (downloading from https://acpica.org/sites/acpica/files/acpica-unix2-20180810.tar.gz)... 100%... hash verified ("b8e1a287557dda6f4b71c4172a7a9123b6ffaf2a")
Downloaded tarballs ... ok
Unpacking and patching ...
* acpica-unix2-20180810.tar.gz
o acpica-unix2-20180810_iasl.patch
Unpacked and patched ... ok
Building packages ...
Building IASL v20180810 for host ... ok
Packages built ... ok
Copied EDK2 tools template ... ok
Cleaning up temporary files... ok

You can now run IASL ACPI compiler from /home/x220/coreboot/util/crossgcc/xgcc.

[x220@x220 coreboot]$ make nconfig

[x220@x220 coreboot]$ make
GEN generated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
GEN build.h
CC bootblock/arch/x86/id.o
CC bootblock/lib/version.o
LINK cbfs/fallback/bootblock.debug
OBJCOPY cbfs/fallback/bootblock.elf
OBJCOPY bootblock.raw.elf
OBJCOPY bootblock.raw.bin
CC romstage/lib/version.o
LINK cbfs/fallback/romstage.debug
OBJCOPY cbfs/fallback/romstage.elf
CC ramstage/lib/version.o
CC smm/lib/version.o
OBJCOPY ramstage/cpu/x86/smm/smm.manual
CC generated/ramstage.o
CC cbfs/fallback/ramstage.debug
Checking out SeaBIOS revision a698c8995ffb2838296ec284fe3c4ad33dfca307
Switched to branch 'master'
Your branch is up to date with 'origin/master'.
Deleted branch coreboot (was a698c89).
Switched to a new branch 'coreboot'
CONFIG SeaBIOS a698c8995ffb2838296ec284fe3c4ad33dfca307
# configuration written to /home/x220/coreboot/payloads/external/SeaBIOS/seabios/.config
MAKE SeaBIOS a698c8995ffb2838296ec284fe3c4ad33dfca307
Build Kconfig config file
Compile checking out/src/misc.o
Compile checking out/src/stacks.o
Compile checking out/src/output.o
Compile checking out/src/string.o
Compile checking out/src/block.o
Compile checking out/src/cdrom.o
Compile checking out/src/disk.o
Compile checking out/src/mouse.o
Compile checking out/src/kbd.o
Compile checking out/src/system.o
Compile checking out/src/serial.o
Compile checking out/src/sercon.o
Compile checking out/src/clock.o
Compile checking out/src/resume.o
Compile checking out/src/pnpbios.o
Compile checking out/src/vgahooks.o
Compile checking out/src/pcibios.o
Compile checking out/src/apm.o
Compile checking out/src/cp437.o
Compile checking out/src/hw/pci.o
Compile checking out/src/hw/timer.o
Compile checking out/src/hw/rtc.o
Compile checking out/src/hw/dma.o
Compile checking out/src/hw/pic.o
Compile checking out/src/hw/ps2port.o
Compile checking out/src/hw/serialio.o
Compile checking out/src/hw/usb.o
Compile checking out/src/hw/usb-uhci.o
Compile checking out/src/hw/usb-ohci.o
Compile checking out/src/hw/usb-ehci.o
Compile checking out/src/hw/usb-hid.o
Compile checking out/src/hw/usb-msc.o
Compile checking out/src/hw/usb-uas.o
Compile checking out/src/hw/blockcmd.o
Compile checking out/src/hw/floppy.o
Compile checking out/src/hw/ata.o
Compile checking out/src/hw/ramdisk.o
Compile checking out/src/hw/lsi-scsi.o
Compile checking out/src/hw/esp-scsi.o
Compile checking out/src/hw/megasas.o
Compile checking out/src/hw/mpt-scsi.o
Compile checking out/src/post.o
Compile checking out/src/e820map.o
Compile checking out/src/malloc.o
Compile checking out/src/romfile.o
Compile checking out/src/x86.o
Compile checking out/src/optionroms.o
Compile checking out/src/pmm.o
Compile checking out/src/font.o
Compile checking out/src/boot.o
Compile checking out/src/bootsplash.o
Compile checking out/src/jpeg.o
Compile checking out/src/bmp.o
Compile checking out/src/tcgbios.o
Compile checking out/src/sha1.o
Compile checking out/src/hw/pcidevice.o
Compile checking out/src/hw/ahci.o
Compile checking out/src/hw/pvscsi.o
Compile checking out/src/hw/usb-xhci.o
Compile checking out/src/hw/usb-hub.o
Compile checking out/src/hw/sdcard.o
Compile checking out/src/fw/coreboot.o
Compile checking out/src/fw/lzmadecode.o
Compile checking out/src/fw/multiboot.o
Compile checking out/src/fw/csm.o
Compile checking out/src/fw/biostables.o
Compile checking out/src/fw/paravirt.o
Compile checking out/src/fw/shadow.o
Compile checking out/src/fw/pciinit.o
Compile checking out/src/fw/smm.o
Compile checking out/src/fw/smp.o
Compile checking out/src/fw/mtrr.o
Compile checking out/src/fw/xen.o
Compile checking out/src/fw/acpi.o
Compile checking out/src/fw/mptable.o
Compile checking out/src/fw/pirtable.o
Compile checking out/src/fw/smbios.o
Compile checking out/src/fw/romfile_loader.o
Compile checking out/src/hw/virtio-ring.o
Compile checking out/src/hw/virtio-pci.o
Compile checking out/src/hw/virtio-blk.o
Compile checking out/src/hw/virtio-scsi.o
Compile checking out/src/hw/tpm_drivers.o
Compile checking out/src/hw/nvme.o
Compiling whole program out/ccode32flat.o
Compiling whole program out/code32seg.o
Compiling whole program out/ccode16.o
Compiling (16bit) out/romlayout.o
Building ld scripts
Version: rel-1.12.0-0-ga698c89
Fixed space: 0xe05b-0x10000 total: 8101 slack: 14 Percent slack: 0.2%
16bit size: 35840
32bit segmented size: 1699
32bit flat size: 31373
32bit flat init size: 51680
Lowmem size: 2240
f-segment var size: 1392
Linking out/rom16.o
Stripping out/rom16.strip.o
Linking out/rom32seg.o
Stripping out/rom32seg.strip.o
Linking out/rom.o
Prepping out/bios.bin.prep
Total size: 127712 Fixed: 70304 Free: 3360 (used 97.4% of 128KiB rom)
Creating out/bios.bin.elf
Compile checking out/vgasrc/vgainit.o
Compile checking out/vgasrc/vgabios.o
Compile checking out/vgasrc/vgafb.o
Compile checking out/vgasrc/swcursor.o
Compile checking out/vgasrc/vgafonts.o
Compile checking out/vgasrc/vbe.o
Compile checking out/vgasrc/stdvga.o
Compile checking out/vgasrc/stdvgamodes.o
Compile checking out/vgasrc/stdvgaio.o
Compile checking out/vgasrc/clext.o
Compile checking out/vgasrc/bochsvga.o
Compile checking out/vgasrc/geodevga.o
Compile checking out/vgasrc/cbvga.o
Compile checking out/vgasrc/bochsdisplay.o
Compile checking out/vgasrc/ramfb.o
Compiling whole program out/vgaccode16.raw.s
Fixup VGA rom assembler
Compiling (16bit) out/vgaentry.o
Linking out/vgarom.o
Version: rel-1.12.0-0-ga698c89
Extracting binary out/vgabios.bin.raw
Finalizing rom out/vgabios.bin
CREATE build/mainboard/lenovo/x220/cbfs-file.54sf79.out (from /home/x220/coreboot/.config)
MICROCODE cpu_microcode_blob.bin
3rdparty/blobs/cpu/intel/model_206ax/microcode.bin 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
OPTION cmos_layout.bin
CC postcar/mainboard/lenovo/x220/static.o
CC postcar/arch/x86/acpi_s3.o
CC postcar/arch/x86/boot.o
CC postcar/arch/x86/cbfs_and_run.o
CC postcar/arch/x86/cbmem.o
CC postcar/arch/x86/cf9_reset.o
CC postcar/arch/x86/cpu_common.o
CC postcar/arch/x86/exit_car.o
CC postcar/arch/x86/gdt_init.o
CC postcar/arch/x86/memcpy.o
CP postcar/arch/x86/memlayout.ld
CC postcar/arch/x86/memmove.o
CC postcar/arch/x86/memset.o
CC postcar/arch/x86/mmap_boot.o
CC postcar/arch/x86/postcar.o
CC postcar/arch/x86/timestamp.o
CC postcar/commonlib/cbfs.o
CC postcar/commonlib/iobuf.o
CC postcar/commonlib/lz4_wrapper.o
CC postcar/commonlib/mem_pool.o
CC postcar/commonlib/region.o
CC postcar/console/console.o
CC postcar/console/die.o
CC postcar/console/init.o
CC postcar/console/post.o
CC postcar/console/printk.o
CC postcar/console/vsprintf.o
CC postcar/console/vtxprintf.o
CC postcar/cpu/intel/car/non-evict/exit_car.o
CC postcar/cpu/intel/model_206ax/stage_cache.o
CC postcar/cpu/x86/lapic/boot_cpu.o
CC postcar/cpu/x86/mtrr/debug.o
CC postcar/cpu/x86/pae/pgtbl.o
CC postcar/cpu/x86/tsc/delay_tsc.o
CC postcar/device/device_const.o
CC postcar/drivers/pc80/rtc/mc146818rtc.o
CC postcar/drivers/pc80/tpm/tis.o
CC postcar/drivers/spi/adesto.o
CC postcar/drivers/spi/amic.o
CC postcar/drivers/spi/atmel.o
CC postcar/drivers/spi/bitbang.o
CC postcar/drivers/spi/eon.o
CC postcar/drivers/spi/gigadevice.o
CC postcar/drivers/spi/macronix.o
CC postcar/drivers/spi/spansion.o
CC postcar/drivers/spi/spi-generic.o
CC postcar/drivers/spi/spi_flash.o
CC postcar/drivers/spi/sst.o
CC postcar/drivers/spi/stmicro.o
CC postcar/drivers/spi/winbond.o
CC postcar/lib/boot_device.o
CC postcar/lib/bootmode.o
CC postcar/lib/cbfs.o
CC postcar/lib/cbmem_common.o
CC postcar/lib/cbmem_console.o
CC postcar/lib/delay.o
CC postcar/lib/ext_stage_cache.o
CC postcar/lib/fmap.o
CC postcar/lib/gcc.o
CC postcar/lib/halt.o
CC postcar/lib/imd.o
CC postcar/lib/imd_cbmem.o
CC postcar/lib/libgcc.o
CC postcar/lib/lzma.o
CC postcar/lib/lzmadecode.o
CC postcar/lib/memchr.o
CC postcar/lib/memcmp.o
CC postcar/lib/prog_loaders.o
CC postcar/lib/prog_ops.o
CP postcar/lib/program.ld
CC postcar/lib/reset.o
CC postcar/lib/rmodule.o
CC postcar/lib/romstage_handoff.o
CC postcar/lib/timestamp.o
CC postcar/lib/version.o
CC postcar/northbridge/intel/sandybridge/ram_calc.o
CC postcar/southbridge/intel/common/pmbase.o
CC postcar/southbridge/intel/common/reset.o
CC postcar/southbridge/intel/common/rtc.o
CC postcar/southbridge/intel/common/spi.o
LINK cbfs/fallback/postcar.debug
IASL build/dsdt.aml

Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20180810
Copyright (c) 2000 - 2018 Intel Corporation

coreboot toolchain v1.53 August 16th, 2018
dsdt.aml 2122: Method(BINF, 2, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml 2640: Method (MLCG, 1)
Remark 2146 - ^ Method Argument is never used (Arg0)

dsdt.aml 2676: Method (WAKE, 1)
Remark 2146 - ^ Method Argument is never used (Arg0)

ASL Input: dsdt.aml - 2897 lines, 49097 bytes, 1300 keywords
AML Output: dsdt.aml - 13778 bytes, 539 named objects, 761 executable opcodes

Compilation complete. 0 Errors, 0 Warnings, 3 Remarks, 349 Optimizations, 1 Constants Folded
IASL build/dsdt.aml disassembled correctly.
HOSTCC cbfstool/cbfstool.o
HOSTCC cbfstool/cbfs_image.o
HOSTCC cbfstool/cbfs-mkstage.o
HOSTCC cbfstool/cbfs-mkpayload.o
HOSTCC cbfstool/fit.o
HOSTCC cbfstool/partitioned_file.o
HOSTCC cbfstool/cbfs.o
HOSTCC cbfstool/fsp_relocate.o
HOSTCC cbfstool/mem_pool.o
HOSTCC cbfstool/region.o
HOSTCC cbfstool/2sha_utility.o
HOSTCC cbfstool/2sha1.o
HOSTCC cbfstool/2sha256.o
HOSTCC cbfstool/2sha512.o
HOSTCC cbfstool/linux_trampoline.o
HOSTCC cbfstool/cbfs-payload-linux.o
HOSTCC cbfstool/compress.o
HOSTCC cbfstool/lz4.o
HOSTCC cbfstool/lz4hc.o
HOSTCC cbfstool/lz4frame.o
HOSTCC cbfstool/xxhash.o
HOSTCC cbfstool/lz4_wrapper.o
HOSTCC cbfstool/lzma.o
HOSTCC cbfstool/LzFind.o
HOSTCC cbfstool/LzmaDec.o
HOSTCC cbfstool/LzmaEnc.o
HOSTCC cbfstool/cbfstool (link)
Created CBFS (capacity = 917464 bytes)
CBFS fallback/romstage
CBFS cpu_microcode_blob.bin
CBFS fallback/ramstage
CBFS vgaroms/seavgabios.bin
CBFS config
CBFS revision
CBFS cmos_layout.bin
CBFS fallback/postcar
CBFS fallback/dsdt.aml
CBFS fallback/payload
CBFS payload_config
CBFS payload_revision
DD Adding Intel Firmware Descriptor
IFDTOOL me.bin -> coreboot.pre
File build/coreboot.pre is 8388608 bytes
File 3rdparty/blobs/mainboard/lenovo/x220/me.bin is 5230592 bytes
Adding 3rdparty/blobs/mainboard/lenovo/x220/me.bin as the Intel ME section of build/coreboot.pre
Writing new image to build/coreboot.pre.new
IFDTOOL gbe.bin -> coreboot.pre
File build/coreboot.pre is 8388608 bytes
File 3rdparty/blobs/mainboard/lenovo/x220/gbe.bin is 8192 bytes
Adding 3rdparty/blobs/mainboard/lenovo/x220/gbe.bin as the GbE section of build/coreboot.pre
Writing new image to build/coreboot.pre.new
IFDTOOL Unlocking Management Engine
File build/coreboot.pre is 8388608 bytes
Writing new image to build/coreboot.pre.new
CBFS coreboot.rom
SeaBIOS Wait up to 3000 ms for PS/2 keyboard controller initialization
CBFSLAYOUT coreboot.rom

This image contains the following sections that can be manipulated with this tool:

'RW_MRC_CACHE' (size 65536, offset 7405568)
'COREBOOT' (CBFS, size 917504, offset 7471104)

It is possible to perform either the write action or the CBFS add/remove actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
CBFSPRINT coreboot.rom

Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 78276 none
cpu_microcode_blob.bin 0x132c0 microcode 25600 none
fallback/ramstage 0x19740 stage 101433 none
vgaroms/seavgabios.bin 0x323c0 raw 27648 none
config 0x39040 raw 425 none
revision 0x39240 raw 570 none
cmos_layout.bin 0x394c0 cmos_layout 1816 none
fallback/postcar 0x39c40 stage 15264 none
fallback/dsdt.aml 0x3d840 raw 13778 none
fallback/payload 0x40e80 simple elf 67325 none
payload_config 0x515c0 raw 1700 none
payload_revision 0x51cc0 raw 236 none
etc/ps2-keyboard-spinup 0x51e00 raw 8 none
(empty) 0x51e40 null 579992 none
bootblock 0xdf800 bootblock 1968 none
HOSTCC cbfstool/ifwitool.o
HOSTCC cbfstool/ifwitool (link)

Built lenovo/x220 (ThinkPad X220)

[x220@x220 ~]
$ sudo flashrom -w build/coreboot.rom -p ch341a_spi -c "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E"


  1. Thanks so much for this guide! Especially the config settings. Only one thing I found out recently was when I upgraded to 16GB of RAM on my x220 that it wouldn't boot until I turned off the "[*] Ignore vendor programmed fuses that limit max. DRAM frequency" setting, rebuilt coreboot, and re-flashed. No idea why that was but everything is running great now.

  2. I am no longer positive the place you are getting your info, however great topic. I must spend a while studying much more or understanding more. Thanks for great info I was on the lookout for this information for my mission.

  3. Thanks for finally writing about > %blog_title% < Liked it!